Verilog Snippets and Notes

A host for some Verilog-snippets written during Lab Sessions of Computer Architecture Course at BITS Pilani.

Consider giving it a ☆ if the repo helps you in any way

Running a file

• Compile the verilog file (one with.v extension) using following command

iverilog -o filename.vvp filename.v

• To see output using $monitor statements run following command

vvp filename.vvp

• To get graphical waveform output, make sure to add following lines in every test branch

initial
    begin
        $dumpfile("filename.vcd");
        $dumpvars;
    end

• To see graphical waveform output

gtkwave filename.vcd

• To include a header file in your program

`include "modulename.v"

Most Common Mistakes in Verilog

1. All keywords should be in lower case.
2. Upper case and lower case are distinct in verilog, it is case sensitive
3. Make sure that the wires are properly declared before usage.
4. Unwanted spaces will put you in trouble ex. endmodule doesn’t have any space in between.
5. Module declaration is a statement terminate it with a semicolon.
6. Module name can’t start with a number and can’t have a special charcters in it.
7. The output ‘x’ indicates that the signal is still unkown and being evaluated.
8. In combinational circuits ‘z’ in the output means the signals are not connected properly.

Labs Breakdown

Lab#	Labsheet	notes	topic
1	link	link	Intro to verilog
2	link	link	Combinational Circuit Modeling
3	link	link	Sequential Circuit Modeling
4	link	link	ALU Design
5	link	link	Register File Implementation
6	link	link	Single Cycle Datapath Design
7	link	link	Multi-Cycle controller Design
8	link	link	Pipeline Design

References

1. Verilog HDL by Samir Palnitkar

Disclaimer

• The codes are not guaranteed to be correct and have not been verified thouroughly, if you find a mistake please feel free to send a PR or contact me via mail.
• All files on this repository are for educational purpose with no intentions of promoting unfair means in any evaluative component

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